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OKI Semiconductor ML9212
GENERAL DESCRIPTION
FEDL9212-01
Issue Date: Nov., 26, 2002
32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming
The ML9212 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to 96 segments, and 10-bit digital dimming circuit. ML9212 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9212 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS.
FEATURES
: 4.5 to 5.5 V * Logic supply voltage (VDD) : 8 to 18 V * Driver supply voltage (VDISP) * Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI = 1/2 duty selectable at "H" level DUP/TRI = 1/3 duty selectable at "L" level * Number of display segments Max. 64-segment display (during 1/2 duty mode) Max. 96-segment display (during 1/3 duty mode) * Master/Slave selectable M/S = Master mode selectable at "H" level M/S = Slave mode selectable at "L" level * Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN * 32-segment driver outputs : IOH = -5 mA at VOH = VDISP-0.8 V (SEG1 to 22) (can be directly connected to VFD tube : IOH = -10 mA at VOH = VDISP-0.8V (SEG23 to 32) and require no external resisters) : IOL = 500 A at VOL = 2 V (SEG1 to 32) * 3-grid pre-driver outputs : IOH = -5.0 mA at VOH = VDISP-0.8 V (require external drivers) IOL = 10 mA at VOL = 2 V * Logic outputs : IOH = -200 A at VOH = VDD-0.8 V IOL = 200 A at VOL = 0.8 V * Built-in digital dimming circuit (10-bit resolution) * Built-in oscillation circuit (external R and C) * Built-in Power-On-Reset circuit * Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K)(ML9212GA)
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ML9212
BLOCK DIAGRAM
SEG1 SEG32 GRID1 GRID2 GRID3
VDISP D-GND VDD L-GND Power On Reset 0H 4H
32 Segment Driver
3 Grid Pre Driver
POR Out1-32 96 to 32 Segment Control in1-32
in1-32
in1-32
POR
Mode Select in1-3
1H 0H
POR
Out1-32 Segment Latch1 in1-32
2H 0H
POR
Out1-32 Segment Latch2 in1-32
3H 0H
POR
Out1-32 Segment Latch3 in1-32
CS CLOCK DATA IN Control
Out1-3 3 bit Shift Register POR
Out1-32 32 bit Shift Register POR
4H
POR
In1-10 Dimming Latch Out1-10
OSC0
OSC POR
10 bit Digital Dimming
DIM IN SYNC IN1 SYNC IN2 M/S DUP/TRI Timing Generator
DIM OUT SYNC OUT1 SYNC OUT2
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PIN CONFIGURATION (TOP VIEW)
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
D-GND
48 SEG18 47 SEG17
SEG16
SEG15
45
56 VDISP
SEG14
44
43 VDISP 42 SEG13 41 SEG12 40 SEG11 39 SEG10 38 SEG9 37 SEG8 36 SEG7 35 SEG6 34 SEG5 33 SEG4 32 SEG3 31 SEG2 30 SEG1 29 NC
55
54
53
52
51
50
49
SEG25 1 SEG26 2 SEG27 3 SEG28 4 SEG29 5 SEG30 6 SEG31 7 SEG32 8 GRID1 9 GRID2 10 GRID3 11 D-GND 12 NC 13 VDD 14 DIM IN 15 SYNC IN 1 16 SYNC IN 2 17 CS 18 CLOCK 19 DATA IN 20 L-GND 21 NC 22 OSC0 23 DUP/TRI 24 M/S 25 SYNC OUT 2 26 SYNC OUT 1 27 DIM OUT 28
NC: No connection (OPEN)
56-pin Plastic QFP
46
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PIN DESCRIPTIONS
Symbol VDISP VDD D-GND L-GND Pin 43, 56 14 12, 49 21 30 to 42, 44 to 48, 50 to 53 Type -- -- -- -- Description Power supply pins for VFD driver circuit. 43 pin and 56 pin should be connected externally. Power supply pin for logic drive. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. 12 pin, 21 pin and 49 pin should be connected externally. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. lOHL -5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. lOHL -10 mA Inverted Grid signal output pins. For pre-driver, the external circuit is required. lOL 10 mA Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. Dimming pulse input. When the slave mode is selected, the pulse width of the all segment output are controlled by a input pulse width of DIM IN. Connect this pin to the master side DIM OUT pin at the slave mode. When the master mode is selected, the input level of this pin is ignored and the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Connect this pin to VDD or L-GND at the master mode.
SEG1 to 22
O
SEG23 to 32
1 to 8, 54, 55
O
GRID1 to 3
9, 10, 11
O
CS CLOCK
18 19
I I
DATA IN
20
I
DUP/TRl
24
I
M/S
25
I
DIM IN
15
I
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ML9212
Symbol
Pin
Type
Description Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1, and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to VDD or L-GND at the master mode. Dimming pulse output. Connect this pin to the slave side DIM IN pin. Synchronous signal output. Connect these pins to the slave side SYNC IN 1, and 2 pins. RC oscillator connecting pins. VDD Oscillation frequency depends OSC0 on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS. R
SYNC IN 1, 2
16, 17
I
DIM OUT SYNC OUT 1, 2
28 26, 27
O O
OSC0
23
I/O
C
NC
13,22,29
-
OPEN pins.
ABSOLUTE MAXIMUM RATING
Parameter Driver Supply Voltage Logic Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VDD VIN PD TSTG Io1 Io2 Output Current Io3 Io4 Condition -- -- -- Ta 105C -- SEG1 to 22 SEG23 to 32 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Ratings -0.3 to +20 -0.3 to +6.5 -0.3 to VDD+0.3 233 -55 to +150 -10.0 to +2.0 -20.0 to +2.0 -10.0 to +20.0 -2.0 to +2.0 Unit V V V mW C mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage Logic Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Symbol VDISP VDD VIH VIL fC Condition -- -- All inputs except OSC0 All inputs except OSC0 -- Min. 8.0 4.5 0.8VDD -- -- Typ. 13.0 5.0 -- -- -- Max. 18.0 5.5 -- 0.2VDD 2.0 Unit V V V V MHz
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Parameter Oscillation Frequency Frame Frequency Operating Temperature
Symbol fOSC fFR TOP
Condition R = 10 k5%, C = 27 pF5% R = 10 k5%, C = 27 pF5% -- 1/3 duty 1/2 duty
Min 2.2 179 268 -40
Typ. 3.3 269 403 --
Max. 4.4 358 538 +105
Unit MHz Hz C
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Ta = -40 to +105C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Symbol VIH VIL IIH IIL VOH1 VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 IDISP Supply Current IDD Applied pin *1) *1) *1) *1) SEG1-22 SEG23-32 GRID1-3 *2) SEG1-22 SEG23-32 GRID1-3 *2) VDISP VDD
VDD = 4.5 V
VDlSP = 9.5V VDISP = 9.5V
Condition -- -- VIH = VDD VIL = GND lOH1 = -5 mA lOH2 = -10 mA lOH3 = -5 mA
VDD = 4.5 V
Min. 0.8VDD -- -1.0 -1.0 VDlSP - 0.8 VDlSP - 0.8 VDlSP - 0.8 VDD - 0.8 -- -- -- -- -- --
Max. -- 0.2VDD +1.0 +1.0 -- -- -- -- 2.0 2.0 2.0 0.8 100 5.0
Unit V V A A V V V V V V V V uA mA
lOH4 = -200 A lOL1 = 500 A lOL2 = 500 A lOL3 = 10 mA lOL4 = 200 A
R = 10 k5%, C = 27 pF5% no load
*1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2
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ML9212
AC Characteristics
Ta = -40 to +105C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) CS Wait Time Output Slew Rate Time VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tRSOFF tR tF tPRZ tPOF CL = 100 pF Condition -- -- -- -- -- -- -- -- tR = 20% to 80% tF = 80% to 20% Min. -- 200 200 200 20 200 200 400 -- -- -- 5.0 Max. 2.0 -- -- -- -- -- -- -- 2.0 2.0 100 -- Unit MHz ns ns ns s ns ns ns s s s ms
Mounted in a unit Mounted in a unit, VDD = 0.0 V
TIMING DIAGRAM
Data Input Timing
tCSS CS 1/fC tCW CLOCK tDS DATA IN VALID VALID tDH VALID VALID tCW tCSH tCSL -0.8VDD -0.2VDD -0.8VDD -0.2VDD -0.8VDD -0.2VDD
Reset Timing
VDD tPRZ tRSOFF CS -0.8VDD -0.0 V tPOF -0.8VDD -0.0 V
Driver Output Timing
tR tF tR -0.8VDISP -0.2VDISP
SEG1-32, GRID1-3
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Output Timing (Duplex Operation) *1bit time = 4/fOSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode
2048 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND VDISP 64 bit times SEG1-32 64 bit times 64 bit times D-GND VDISP D-GND VDD DIM OUT L-GND VDD SYNC OUT1 L-GND VDD L-GND
GRID3
SYNC OUT2
Output Timing (Triplex Operation) *1bit time = 4/fOSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode
3072 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND GRID3 64 bit times SEG1-32 D-GND DIM OUT VDD L-GND SYNC OUT1 VDD L-GND SYNC OUT2 VDD L-GND 64 bit times 1016 bit times 64 bit times VDISP D-GND VDISP
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FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, ML9212 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * GRID1 outputs are set to Low level. * GRID2 to 3 outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows:
FUNCTION MODE 0 1 2 3 4 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input FUNCTION DATA M0 0 1 0 1 0 M1 0 0 1 1 0 M2 0 0 0 0 1
Segment Data Input [Function Mode: 0 to 3] * ML9212 receives the segment data when function mode 0 to 3 are selected. * The same segment data is transferred to the 3 segment data latches corresponding to GRID1 to 3 at the same time when the function mode 0 is selected. * The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. * Segment output (SEG1 to 32) becomes High level (lightning) when the segment data (S1 to S32) is set to "1". [Data Format] Input Data Segment Data Mode Data
Bit Input DATA 1 S1 2 S2
: 35 bits : 32 bits : 3 bits
3 S3 4 S4 29 S29 30 S30 31 S31 32 S32 33 M0 34 M1 35 M2
Segment Data (32 bits)
Mode Data (3 bits)
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ML9212
[Bit correspondence between segment output and segment data]
SEG n
Segment data
1
S1
2
S2
3
S3
4
S4
5
S5
6
S6
7
S7
8
S8
9
S9
10
S10
11
S11
12
S12
13
S13
14
S14
15
S15
16
S16
SEG n
Segment data
17
S17
18
S18
19
S19
20
S20
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
28
S28
29
S29
30
S30
31
S31
32
S32
Digital Dimming Data Input [Function Mode: 4] * ML9212 receives the digital dimming data when function mode 4 is selected. * The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. * The 10-bit digital dimming data is input from LSB. [Data Format] Input Data Digital Dimming Data Mode Data
Bit Input DATA 1 D1 LSB 2 D2 3 D3
: 13 bits : 10 bits : 3 bits
4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 D10 MSB 11 M0 12 M1 13 M2
Digital Dimming Data (10 bits)
Mode Data (3 bits)
(LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 ... 0 1 1 ... 1
Dimming Data D5 0 0 1 1 1 1 D6 0 0 1 1 1 1 D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1
(MSB) D10 0 0 1 1 1 1
Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 ... ...
Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: * The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. * The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming circuit. * The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator.
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ML9212
Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: * The internal dimming circuit is ignored. * The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal. * The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. * The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level.
[Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] SYNC IN 1 0 1 0 1 SYNC IN 2 0 0 1 1 Segment Latch No Latch1 Latch2 Latch3 GRID No GRID1 GRID2 GRID3 [Correspondence between DIM IN and SEG1 to 32] DIM IN 0 1 Note: Low: Lights OFF High: Lights ON SEG1 to 32 Low High
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APPLICATION CIRCUITS
VDD
VDISP GRID2 GRID3
S1 S2 S3
VDD
VDISP VDD SEG1 ML9212 (MASTER) SEG32 GRID1 DUP/TRI VDISP VDD SEG1 ML9212 (SLAVE) VDD SEG32 DUP/TRI GRID1 GRID2 M/S GND GRID3
S62 S63 S64
M/S
SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2
GND G1 G2 DIM OUT DIM OUT
SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2
Duplex VF Tube Ef
DIM IN CS DATA IN CLOCK DIM IN CS DATA IN CLOCK R C D-GND GND OSC 0 L-GND
1. Circuit for the duplex VFD tube with 128 segments (2 Grid x 64 Anode)
Microcontroller
R
C
OSC 0 L-GND D-GND
GND
GND
FEDL9212-01
ML9212
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2.
VDISP SEG1
VDD M/S DUP/TRI
S1 S2 S3
VDD ML9212 (SLAVE)
VDISP GRID2 GRID3 GND
SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2
VDD
GND
VDISP VDD SEG1 ML9212 (MASTER) SEG32 M/S GRID1 SEG32 GRID1 GRID2 GRID3
S62 S63 S64
DUP/TRI
SYNC IN 1 SYNC OUT1 SYNC IN 2 SYNC OUT2
DIM OUT DIM OUT
G1 G2 G3
Triplex VF Tube Ef
DIM IN CS DATA IN CLOCK R C GND OSC 0 L-GND D-GND
DIM IN CS DATA IN CLOCK
Circuit for the triplex VFD tube with 192 segments (3 Grid x 64 Anode)
Microcontroller
R
C
OSC 0 L-GND D-GND
GND
GND FEDL9212-01
ML9212
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ML9212
NOTES ON TURNING POWER ON/OFF
* Connect L-GND and D-GND externally to be an equal potential voltage. * To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply.
[Voltage] VDISP VDD [Time]
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REVISION HISTORY
Document No.
FEDL9212-01
Date
Nov., 26, 2002
Page Previous Current Edition Edition
- -
Description
Final edition 1
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ML9212
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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